The present invention relates to semiconductor based memory devices, and in particular to testing fuses in integrated memory circuits.
As the number of electronic elements contained on semiconductor integrated circuits continues to increase, the problems of reducing and eliminating defects in the elements become more difficult. To achieve higher electronic element population densities, circuit designers strive to reduce the size of the individual elements to maximize available die real estate, to increase speed of operation, to increase circuit density per chip, and the like. The reduced size of individual elements, however, makes these elements increasingly susceptible to defects caused by material impurities during fabrication. These defects can be identified upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective circuits is economically undesirable, particularly if only a small number of elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option. To reduce the amount of semiconductor scrap, redundant elements are provided on the circuit. If a primary element is determined to be defective, a redundant element can be substituted for the defective element. Substantial reductions in scrap can be achieved by using redundant elements.
One type of integrated circuit device which uses redundant circuit elements is memory integrated circuits, such as, for example, dynamic random access memories (DRAMs), static random access memories (SRAMs), video random access memories (VRAMs), erasable programmable read only memories (EPROMs), synchronous dynamic random access memories (SDRAMs), FLASH memories, and other memory types. Typical integrated memory circuits comprise millions of equivalent memory cells arranged in arrays of addressable rows and columns. The rows and columns of memory cells are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced.
Because the individual primary circuit elements (rows or columns) of an integrated memory circuit are separately addressable, replacing a defective circuit element typically entails programming fuses to cause a redundant circuit element to respond to the address of the defective primary circuit element. This process is very effective for permanently replacing defective primary circuit elements.
In the case of DRAMs, for example, a particular memory cell is selected by first providing a unique row address of the row in which the particular memory cell is located and subsequently providing a unique column address of the column in which the particular memory cell is located. Redundancy circuitry must recognize the address of the defective primary circuit element and reroute all signals to the redundant circuit element when the address to the defective primary circuit element is presented by the user. Therefore, a number of fuses or antifuses are associated with each redundant circuit element. The possible combinations of programmed fuses corresponding to each redundant circuit element represent unique addresses of all primary circuit elements for which a corresponding redundant circuit element may be substituted. While antifuses are described, fuses will function equally as well in the circuit.
Antifuses are typically fabricated with a structure similar to that of a capacitor, such that two conductive electrical terminals are separated by a dielectric layer. In the unprogrammed state, in which the antifuse is fabricated, there is a high resistance between the terminals, while in the programmed state, there is low resistance. To program an antifuse, a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals.
All antifuses are tested to ensure that they are properly programmed. A prior art technique for testing antifuses is shown in FIG. 1, which shows two reference nodes, SGND node 10 and node 20. The SGND node 10 is also in electrical communication with the input of a testing circuit, which is a comparator 30 which compares a hard wired reference voltage to the voltage on the SGND node 10. A precharge voltage 40 is applied to the SGND node 10. A switch 45 is interposed between precharge voltage 40 and SGND node 10 to turn the precharge voltage 40 on and off. The node 20 is connected to ground. Antifuses 50 are electrically interposed between the SGND node 10 and the node 20.
Fuse F1 is one of the fuses in bank B1. In order to test whether a good program has been achieved for fuse F1, switch SB1 for the bank B1 is actuated while switch SF1 is enabled. Having both switch SB1 and switch SF1 simultaneously actuated creates a direct path from SGND node 10 to node 20. Because the fuse F1 has resistance and the bus to which it is connected has capacitance, upon actuation of both switch SB1 and switch SF1, the voltage of SGND node 10 decays in a manner consistent with an RC circuit. Prior to the actuation of switch SB1 and switch SF1, output of the comparator 30 is in a tri-state condition; however, as soon as switch SB1 and switch SF1 are actuated, the output of comparator 30 switches low. If fuse F1 was properly programmed, the output of comparator 30 will switch back high at or before a switch time period tfuse. If the output of comparator 30 does not switch back high at or before switch time period tfuse, then fuse F1 was not properly programmed.
The switch time period tfuse is typically determined by performing the following steps for a statistically valid number of fuses. First, the resistance of a fuse is measured. Techniques for measuring resistance are well known in the art; however, one way of measuring fuse resistance is by applying a voltage across a fuse, measuring the resulting current through the fuse, and calculating the resistance using Ohm""s law. Second, a measurement is taken of the time it takes from when both the bank switch (such as, for example, SBn or SB1) and the fuse switch (such as, for example, SF1, SF2, SFx, etc.) are actuated for the output of the comparator 30 (as shown in FIG. 1) to swing to the high state. As an example, if fuse F2 is being tested, both bank switch SB1 and fuse switch SF2 must be actuated. The measurement time obtained is referred to as a ttest value. Third, the individual ttest value for a particular fuse is plotted against the resistance value for such particular fuse, and this step is performed for all measured fuses. Fourth, a decision is made as to what resistance value is indicative of a fuse that has been programmed properly. For example, it may be decided that a resistance value of 300 Kxcexa9 or less indicated that the fuse being tested has been properly programmed. Finally, from the plot of ttest versus resistance, as described in the third step above, it is determined at or under which ttest value the comparator output switched for a majority of the fuses measured having resistance values of 300 Kxcexa9 or less.
The process of collecting and analyzing data for a statistically valid number of fuses can be lengthy. Accordingly, such process is performed offline. After data regarding fuse test times and resistance values are collected and analyzed, and a switch time period tfuse is established, individual fuses are then tested in accordance with the circuit shown in FIG. 1. This testing is performed during manufacturing or as the fuses are programmed.
Moreover, the comparator 30 has a reference 55 which, in the prior art, is hardwired to a particular voltage value. Hence, the switch time period tfuse is highly dependent on the voltage value to which the reference in the comparator 30 is connected. For example, suppose the reference in the comparator 30 is hardwired to 2.5 V, so that when the voltage level on SGND node 10 drops below 2.5 V the output of the comparator 30 switches high. It is possible for the output of the comparator 30 to switch even at a reference voltage greater than 2.5 V (e.g. 3.0 V), thus decreasing the testing time required. However, because the reference in the comparator 30 is hardwired to a particular voltage, it is difficult to change the reference voltage in the event tighter control over testing time is desired.
Accordingly, there is a need for testing fuses without having to collect sample points. There is further a need to make the process of testing fuses faster in order to save testing time during manufacture.
The present invention is directed to a method and circuit for testing fuses in memory integrated circuits such as those discussed above. One embodiment of the invention is a circuit comprising a test bank of control resistors and a testing circuit, wherein the bank of control resistors establishes a test period of all fuses being tested. In another aspect of the invention, the testing circuit comprises a comparator having a reference voltage for comparison to a node voltage, wherein an external access to the reference of the comparator is provided. This external access to the reference of the comparator permits the minimization of test times.
The step of determining the testing time for a fuse comprises the steps of allowing to decay the voltage applied to the node, and waiting a time period for the voltage applied to the node to decay to a voltage less than or equal to the reference voltage applied to the comparator. In another aspect of the invention, the method includes, after the step of comparing the testing time for the fuse against the testing time for the control resistor, the step of deciding whether the testing time for the fuse meets predetermined specification parameters based on the testing time for the control resistor. The use of the control resistor obviates the need for the prior art technique of collecting and analyzing data for a statistically valid number of fuses.